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| author | Robin Morisset <morisset@google.com> | 2014-09-23 18:33:21 +0000 |
|---|---|---|
| committer | Robin Morisset <morisset@google.com> | 2014-09-23 18:33:21 +0000 |
| commit | a7b357fed197d80f89558c0e73f6ff6623e741dd (patch) | |
| tree | aeb4116b4507538181e85b7fc452ebd5f209024c /llvm/lib/Target/ARM/ARMISelLowering.cpp | |
| parent | acee96ae5290a965e20f1cb938002d9fd4012075 (diff) | |
| download | bcm5719-llvm-a7b357fed197d80f89558c0e73f6ff6623e741dd.tar.gz bcm5719-llvm-a7b357fed197d80f89558c0e73f6ff6623e741dd.zip | |
Just add a fixme about a possibly faster implementation of some atomic loads on some ARM processors
llvm-svn: 218326
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index ca6b614ce2e..97b62264462 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -11086,6 +11086,9 @@ bool ARMTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const { // are doomed anyway, so defer to the default libcall and blame the OS when // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit // anything for those. +// FIXME: ldrd and strd are atomic if the CPU has LPAE (e.g. A15 has that +// guarantee, see DDI0406C ARM architecture reference manual, +// sections A8.8.72-74 LDRD) bool ARMTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const { unsigned Size = LI->getType()->getPrimitiveSizeInBits(); return (Size == 64) && !Subtarget->isMClass(); |
