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authorPat Gavlin <pagavlin@microsoft.com>2015-07-09 17:40:29 +0000
committerPat Gavlin <pagavlin@microsoft.com>2015-07-09 17:40:29 +0000
commita717f255b6e1c6cfdb7c96d2b9619e8c6edaa074 (patch)
treee36d1f779d9147d3ae496539571e14eec11c0fc9 /llvm/lib/Target/ARM/ARMISelLowering.cpp
parente2361d4a184a57fb3e96294918dfbdc9f7cb2d72 (diff)
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Allow {e,r}bp as the target of {read,write}_register.
This patch allows the read_register and write_register intrinsics to read/write the RBP/EBP registers on X86 iff the targeted register is the frame pointer for the containing function. Differential Revision: http://reviews.llvm.org/D10977 llvm-svn: 241827
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMISelLowering.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 9f688a456b4..e747ab0daca 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -4101,8 +4101,8 @@ SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
// FIXME? Maybe this could be a TableGen attribute on some registers and
// this table could be generated automatically from RegInfo.
-unsigned ARMTargetLowering::getRegisterByName(const char* RegName,
- EVT VT) const {
+unsigned ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT,
+ SelectionDAG &DAG) const {
unsigned Reg = StringSwitch<unsigned>(RegName)
.Case("sp", ARM::SP)
.Default(0);
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