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author | Chris Lattner <sabre@nondot.org> | 2008-07-11 20:53:00 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2008-07-11 20:53:00 +0000 |
commit | 9fc580f2d0afde49be61e3061f3098dac59e1d69 (patch) | |
tree | f49ea57a7b21d4034ee932b8526a0f430cbcf3cd /llvm/lib/Target/ARM/ARMISelLowering.cpp | |
parent | 0597e5b697679d65e0a796244396c84a80ae4094 (diff) | |
download | bcm5719-llvm-9fc580f2d0afde49be61e3061f3098dac59e1d69.tar.gz bcm5719-llvm-9fc580f2d0afde49be61e3061f3098dac59e1d69.zip |
add support for returning i128, PR2532.
llvm-svn: 53472
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
-rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 07c88fdfa43..15c225aebe7 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -685,6 +685,20 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1); } break; + case 9: // i128 -> 4 regs + Copy = DAG.getCopyToReg(Chain, ARM::R3, Op.getOperand(7), SDOperand()); + Copy = DAG.getCopyToReg(Copy , ARM::R2, Op.getOperand(5), Copy.getValue(1)); + Copy = DAG.getCopyToReg(Copy , ARM::R1, Op.getOperand(3), Copy.getValue(1)); + Copy = DAG.getCopyToReg(Copy , ARM::R0, Op.getOperand(1), Copy.getValue(1)); + // If we haven't noted the R0+R1 are live out, do so now. + if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { + DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0); + DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1); + DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R2); + DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R3); + } + break; + } //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag |