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author | Eli Friedman <efriedma@codeaurora.org> | 2017-03-25 00:13:24 +0000 |
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committer | Eli Friedman <efriedma@codeaurora.org> | 2017-03-25 00:13:24 +0000 |
commit | 95ddd18703f6086cf2b54daa059228196fe8f0a6 (patch) | |
tree | 69ebc668886c67173d82c95131cb1d7a273c75f8 /llvm/lib/Target/ARM/ARMISelLowering.cpp | |
parent | dbc94db3f3b55304ede10bf1e6bd711f4bbe2769 (diff) | |
download | bcm5719-llvm-95ddd18703f6086cf2b54daa059228196fe8f0a6.tar.gz bcm5719-llvm-95ddd18703f6086cf2b54daa059228196fe8f0a6.zip |
[ARM] Fix mixup between Lo and Hi in SMLALBB formation.
llvm-svn: 298752
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
-rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index ea438a19b0c..723b2fb451b 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -9517,19 +9517,19 @@ static SDValue AddCombineTo64BitSMLAL16(SDNode *AddcNode, SDNode *AddeNode, // be sign extended somehow or SRA'd into 32-bit values // (addc (adde (mul 16bit, 16bit), lo), hi) SDValue Mul = AddcNode->getOperand(0); - SDValue Hi = AddcNode->getOperand(1); + SDValue Lo = AddcNode->getOperand(1); if (Mul.getOpcode() != ISD::MUL) { - Hi = AddcNode->getOperand(0); + Lo = AddcNode->getOperand(0); Mul = AddcNode->getOperand(1); if (Mul.getOpcode() != ISD::MUL) return SDValue(); } SDValue SRA = AddeNode->getOperand(0); - SDValue Lo = AddeNode->getOperand(1); + SDValue Hi = AddeNode->getOperand(1); if (SRA.getOpcode() != ISD::SRA) { SRA = AddeNode->getOperand(1); - Lo = AddeNode->getOperand(0); + Hi = AddeNode->getOperand(0); if (SRA.getOpcode() != ISD::SRA) return SDValue(); } |