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| author | Tim Northover <tnorthover@apple.com> | 2013-07-01 14:48:48 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2013-07-01 14:48:48 +0000 |
| commit | 953abab40ae89d546a379fa97afe6dea483e851a (patch) | |
| tree | 5db8f9756cabd9087db5f0a5ed8455bab444769b /llvm/lib/Target/ARM/ARMISelLowering.cpp | |
| parent | 8a4e24ea8b9d7059fa0a8b0a3ce3b838115dcc4a (diff) | |
| download | bcm5719-llvm-953abab40ae89d546a379fa97afe6dea483e851a.tar.gz bcm5719-llvm-953abab40ae89d546a379fa97afe6dea483e851a.zip | |
ARM: relax the atomic release barrier to "dmb ishst"
I believe the full "dmb ish" barrier is not required to guarantee release
semantics for atomic operations. The weaker "dmb ishst" prevents previous
operations being reordered with a store executed afterwards, which is enough.
A key point to note (fortunately already correct) is that this barrier alone is
*insufficient* for sequential consistency, no matter how liberally placed.
llvm-svn: 185339
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index ff8571ba033..370962dfa5d 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -2557,8 +2557,12 @@ static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, DAG.getConstant(0, MVT::i32)); } + ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1)); + AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue()); + unsigned Domain = Ord == Release ? ARM_MB::ISHST : ARM_MB::ISH; + return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0), - DAG.getConstant(ARM_MB::ISH, MVT::i32)); + DAG.getConstant(Domain, MVT::i32)); } static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG, |
