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| author | Evan Cheng <evan.cheng@apple.com> | 2011-09-28 23:16:31 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-09-28 23:16:31 +0000 |
| commit | 8156376aa9d750f3db534b82ab15a4b3f02ef16c (patch) | |
| tree | 41dd2dd87f59429a3430cb063f21f7976bc13b59 /llvm/lib/Target/ARM/ARMISelLowering.cpp | |
| parent | 011824f74728ee11ff9659191bdede36ec2062a8 (diff) | |
| download | bcm5719-llvm-8156376aa9d750f3db534b82ab15a4b3f02ef16c.tar.gz bcm5719-llvm-8156376aa9d750f3db534b82ab15a4b3f02ef16c.zip | |
Tighten a ARM dag combine condition to avoid an identity transformation, which
ends up introducing a cycle in the DAG.
rdar://10196296
llvm-svn: 140733
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 9f313859d56..54f8aaa6d3f 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -7344,7 +7344,7 @@ ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const { // movne r0, y /// FIXME: Turn this into a target neutral optimization? SDValue Res; - if (CC == ARMCC::NE && FalseVal == RHS) { + if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) { Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc, N->getOperand(3), Cmp); } else if (CC == ARMCC::EQ && TrueVal == RHS) { |
