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authorMatt Arsenault <Matthew.Arsenault@amd.com>2017-12-14 22:34:10 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2017-12-14 22:34:10 +0000
commit7d7adf4f2e4e50f738a5f692e6f011dcfca6b070 (patch)
treedf846d9653c67e5bcd684da57d8dc97665c057b3 /llvm/lib/Target/ARM/ARMISelLowering.cpp
parentc7bc461298d540cefec9ffe370f68dfbca367e8b (diff)
downloadbcm5719-llvm-7d7adf4f2e4e50f738a5f692e6f011dcfca6b070.tar.gz
bcm5719-llvm-7d7adf4f2e4e50f738a5f692e6f011dcfca6b070.zip
TLI: Allow using PSV for intrinsic mem operands
llvm-svn: 320756
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMISelLowering.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index f64cb61cf20..f60500d4819 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -13588,6 +13588,7 @@ bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
/// specified in the intrinsic calls.
bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
const CallInst &I,
+ MachineFunction &MF,
unsigned Intrinsic) const {
switch (Intrinsic) {
case Intrinsic::arm_neon_vld1:
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