Revert "Adding support for llvm.arm.neon.vaddl[su].* and"

This reverts r170694.  The operations can be represented in IR without
adding any new intrinsics.

llvm-svn: 170765

1 files changed, 0 insertions, 18 deletions

diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 1105f412cce..8034ce16043 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -1007,10 +1007,6 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case ARMISD::VTBL2:         return "ARMISD::VTBL2";
   case ARMISD::VMULLs:        return "ARMISD::VMULLs";
   case ARMISD::VMULLu:        return "ARMISD::VMULLu";
-  case ARMISD::VADDLs:        return "ARMISD::VADDLs";
-  case ARMISD::VADDLu:        return "ARMISD::VADDLu";
-  case ARMISD::VSUBLs:        return "ARMISD::VSUBLs";
-  case ARMISD::VSUBLu:        return "ARMISD::VSUBLu";
   case ARMISD::UMLAL:         return "ARMISD::UMLAL";
   case ARMISD::SMLAL:         return "ARMISD::SMLAL";
   case ARMISD::BUILD_VECTOR:  return "ARMISD::BUILD_VECTOR";
@@ -2433,20 +2429,6 @@ ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
     return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(),
                        Op.getOperand(1), Op.getOperand(2));
   }
-  case Intrinsic::arm_neon_vaddls:
-  case Intrinsic::arm_neon_vaddlu: {
-    unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vaddls)
-      ? ARMISD::VADDLs : ARMISD::VADDLu;
-    return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(),
-                       Op.getOperand(1), Op.getOperand(2));
-  }
-  case Intrinsic::arm_neon_vsubls:
-  case Intrinsic::arm_neon_vsublu: {
-    unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vsubls)
-      ? ARMISD::VSUBLs: ARMISD::VSUBLu;
-    return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(),
-                       Op.getOperand(1), Op.getOperand(2));
-  }
   }
 }