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| author | Christian Pirker <cpirker@a-bix.com> | 2014-05-14 16:59:44 +0000 |
|---|---|---|
| committer | Christian Pirker <cpirker@a-bix.com> | 2014-05-14 16:59:44 +0000 |
| commit | 6692e7c11689d31405c9912380f6a041edad6fb3 (patch) | |
| tree | 4a32c3560f84f10d582e95efea678542c572a427 /llvm/lib/Target/ARM/ARMISelLowering.cpp | |
| parent | 85cdab63c49317467586502931dcc1d00404ffa7 (diff) | |
| download | bcm5719-llvm-6692e7c11689d31405c9912380f6a041edad6fb3.tar.gz bcm5719-llvm-6692e7c11689d31405c9912380f6a041edad6fb3.zip | |
ARM-BE: test files for vector argument passing
Reviewed at http://reviews.llvm.org/D3766
llvm-svn: 208793
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index e8e28cac206..e7ffeee8f92 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -3965,7 +3965,8 @@ static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) { // Turn f64->i64 into VMOVRRD. if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) { SDValue Cvt; - if (TLI.isBigEndian() && SrcVT.isVector()) + if (TLI.isBigEndian() && SrcVT.isVector() && + SrcVT.getVectorNumElements() > 1) Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op)); |
