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| author | Tim Northover <tnorthover@apple.com> | 2017-04-20 21:56:52 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2017-04-20 21:56:52 +0000 |
| commit | 46e58354daa0e6508a25e3e74b926b8eb6374ccd (patch) | |
| tree | 65a5169ec9c375748b55a07b92fcab15777388ed /llvm/lib/Target/ARM/ARMISelLowering.cpp | |
| parent | 906ffb7b8f8e5cb767a4083a44f69684bb42f3ae (diff) | |
| download | bcm5719-llvm-46e58354daa0e6508a25e3e74b926b8eb6374ccd.tar.gz bcm5719-llvm-46e58354daa0e6508a25e3e74b926b8eb6374ccd.zip | |
ARM: lower "fence singlethread" to a pure compiler barrier.
Single-threaded fences aren't required to provide any synchronization with
other processing elements so there's no need for a DMB. They should still be a
barrier for compiler optimizations though.
llvm-svn: 300904
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 165e9b7378c..0f8cdad983d 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -3358,8 +3358,12 @@ ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) { - // FIXME: handle "fence singlethread" more efficiently. SDLoc dl(Op); + ConstantSDNode *ScopeN = cast<ConstantSDNode>(Op.getOperand(2)); + auto Scope = static_cast<SynchronizationScope>(ScopeN->getZExtValue()); + if (Scope == SynchronizationScope::SingleThread) + return Op; + if (!Subtarget->hasDataBarrier()) { // Some ARMv6 cpus can support data barriers with an mcr instruction. // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get |
