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| author | Rafael Espindola <rafael.espindola@gmail.com> | 2010-07-21 11:38:30 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2010-07-21 11:38:30 +0000 |
| commit | 4277e14dc41636601ce98e736a740ddfc6ca6e10 (patch) | |
| tree | 4b6e7e94b4228abad7c5b3a73513b5bc142583cd /llvm/lib/Target/ARM/ARMISelLowering.cpp | |
| parent | 930894fe6174a5ac898e81cba8113596a1beafa9 (diff) | |
| download | bcm5719-llvm-4277e14dc41636601ce98e736a740ddfc6ca6e10.tar.gz bcm5719-llvm-4277e14dc41636601ce98e736a740ddfc6ca6e10.zip | |
Fix calling convention on ARM if vfp2+ is enabled.
llvm-svn: 109009
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 733042266db..5888c1bf38a 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -831,8 +831,9 @@ static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT, CCState &State, bool CanFail) { static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; + static const unsigned ShadowRegList[] = { ARM::R0, ARM::R1 }; - unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2); + unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2); if (Reg == 0) { // For the 2nd half of a v2f64, do not just fail. if (CanFail) @@ -850,6 +851,9 @@ static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT, if (HiRegList[i] == Reg) break; + unsigned T = State.AllocateReg(LoRegList[i]); + assert(T == LoRegList[i] && "Could not allocate register"); + State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], LocVT, LocInfo)); |
