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| author | Zvi Rackover <zvi.rackover@intel.com> | 2017-07-26 08:06:58 +0000 |
|---|---|---|
| committer | Zvi Rackover <zvi.rackover@intel.com> | 2017-07-26 08:06:58 +0000 |
| commit | 1b73682243b2a21832169ef1faf88f1b1508255d (patch) | |
| tree | c2786a72fb331b1f2ea0bf334213612046ffa02a /llvm/lib/Target/ARM/ARMISelLowering.cpp | |
| parent | 60bc7e0f0aaaa4a121432e2683d446d082e4cd91 (diff) | |
| download | bcm5719-llvm-1b73682243b2a21832169ef1faf88f1b1508255d.tar.gz bcm5719-llvm-1b73682243b2a21832169ef1faf88f1b1508255d.zip | |
TargetLowering: Change isShuffleMaskLegal's mask argument type to ArrayRef<int>. NFCI.
Changing mask argument type from const SmallVectorImpl<int>& to
ArrayRef<int>.
This came up in D35700 where a mask is received as an ArrayRef<int> and
we want to pass it to TargetLowering::isShuffleMaskLegal().
Also saves a few lines of code.
llvm-svn: 309085
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 6d9a32c9956..a6317957b68 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -6520,9 +6520,7 @@ SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op, /// support *some* VECTOR_SHUFFLE operations, those with specific masks. /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values /// are assumed to be legal. -bool -ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, - EVT VT) const { +bool ARMTargetLowering::isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const { if (VT.getVectorNumElements() == 4 && (VT.is128BitVector() || VT.is64BitVector())) { unsigned PFIndexes[4]; |
