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authorEric Christopher <echristo@apple.com>2010-08-20 00:36:24 +0000
committerEric Christopher <echristo@apple.com>2010-08-20 00:36:24 +0000
commit985d9e4ea8879bc173740eaab848a8b50ee626d6 (patch)
tree5040219a5cffb3006d759937a4fdc399f6e29acf /llvm/lib/Target/ARM/ARMFastISel.cpp
parentf85b0b866c23a141083d1c5daa639e9411d96d15 (diff)
downloadbcm5719-llvm-985d9e4ea8879bc173740eaab848a8b50ee626d6.tar.gz
bcm5719-llvm-985d9e4ea8879bc173740eaab848a8b50ee626d6.zip
Fix loop conditionals (MO.isDef() asserts that it's a reg) and
move some constraints around. llvm-svn: 111594
Diffstat (limited to 'llvm/lib/Target/ARM/ARMFastISel.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMFastISel.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp
index a61fca1f252..6281c3a3b0b 100644
--- a/llvm/lib/Target/ARM/ARMFastISel.cpp
+++ b/llvm/lib/Target/ARM/ARMFastISel.cpp
@@ -122,7 +122,8 @@ bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
// Look to see if our OptionalDef is defining CPSR or CCR.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (MO.isDef() && MO.isReg() && MO.getReg() == ARM::CPSR)
+ if (!MO.isReg() || !MO.isDef()) continue;
+ if (MO.getReg() == ARM::CPSR)
*CPSR = true;
}
return true;
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