From 985d9e4ea8879bc173740eaab848a8b50ee626d6 Mon Sep 17 00:00:00 2001 From: Eric Christopher Date: Fri, 20 Aug 2010 00:36:24 +0000 Subject: Fix loop conditionals (MO.isDef() asserts that it's a reg) and move some constraints around. llvm-svn: 111594 --- llvm/lib/Target/ARM/ARMFastISel.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'llvm/lib/Target/ARM/ARMFastISel.cpp') diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp index a61fca1f252..6281c3a3b0b 100644 --- a/llvm/lib/Target/ARM/ARMFastISel.cpp +++ b/llvm/lib/Target/ARM/ARMFastISel.cpp @@ -122,7 +122,8 @@ bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) { // Look to see if our OptionalDef is defining CPSR or CCR. for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (MO.isDef() && MO.isReg() && MO.getReg() == ARM::CPSR) + if (!MO.isReg() || !MO.isDef()) continue; + if (MO.getReg() == ARM::CPSR) *CPSR = true; } return true; -- cgit v1.2.3