diff options
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index de8a04632f5..222aa85856a 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -927,25 +927,25 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, copyToCPSR(MBB, I, SrcReg, KillSrc, Subtarget); return; } else if (DestReg == ARM::VPR) { - assert(ARM::GPRPairRegClass.contains(SrcReg)); + assert(ARM::GPRRegClass.contains(SrcReg)); BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_P0), DestReg) .addReg(SrcReg, getKillRegState(KillSrc)) .add(predOps(ARMCC::AL)); return; } else if (SrcReg == ARM::VPR) { - assert(ARM::GPRPairRegClass.contains(DestReg)); + assert(ARM::GPRRegClass.contains(DestReg)); BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_P0), DestReg) .addReg(SrcReg, getKillRegState(KillSrc)) .add(predOps(ARMCC::AL)); return; } else if (DestReg == ARM::FPSCR_NZCV) { - assert(ARM::GPRPairRegClass.contains(SrcReg)); + assert(ARM::GPRRegClass.contains(SrcReg)); BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_FPSCR_NZCVQC), DestReg) .addReg(SrcReg, getKillRegState(KillSrc)) .add(predOps(ARMCC::AL)); return; } else if (SrcReg == ARM::FPSCR_NZCV) { - assert(ARM::GPRPairRegClass.contains(DestReg)); + assert(ARM::GPRRegClass.contains(DestReg)); BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_FPSCR_NZCVQC), DestReg) .addReg(SrcReg, getKillRegState(KillSrc)) .add(predOps(ARMCC::AL)); |
