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| author | Valery Pykhtin <Valery.Pykhtin@amd.com> | 2016-04-07 13:41:51 +0000 |
|---|---|---|
| committer | Valery Pykhtin <Valery.Pykhtin@amd.com> | 2016-04-07 13:41:51 +0000 |
| commit | e23b6deb01e0e68734814ad48ab6de4980a8cd6b (patch) | |
| tree | a0953e7b666b7426a3cc473b3b00556de54c4f8e /llvm/lib/Target/AMDGPU | |
| parent | af16b958c0a0746f3b3fc354443a6b16ff83a7ee (diff) | |
| download | bcm5719-llvm-e23b6deb01e0e68734814ad48ab6de4980a8cd6b.tar.gz bcm5719-llvm-e23b6deb01e0e68734814ad48ab6de4980a8cd6b.zip | |
[AMDGPU] fix readlane/readfirstlane src vgpr operand type.
For VGPR_32 operand disassembler expects a VGPR register encoded as 0..255 (enum8 src operand).
readfirstlane/readline actually has enum9 operand and this change fixes VGPR_32 to VS_32 (enum9 encoding).
Differential Revision: http://reviews.llvm.org/D18696
llvm-svn: 265670
Diffstat (limited to 'llvm/lib/Target/AMDGPU')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstructions.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 88f1f0c8a8d..2d8651b25a3 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -1205,7 +1205,7 @@ let Uses = [EXEC] in { def V_READFIRSTLANE_B32 : VOP1 < 0x00000002, (outs SReg_32:$vdst), - (ins VGPR_32:$src0), + (ins VS_32:$src0), "v_readfirstlane_b32 $vdst, $src0", [] >; @@ -1579,7 +1579,7 @@ defm V_READLANE_B32 : VOP2SI_3VI_m < vop3 <0x001, 0x289>, "v_readlane_b32", (outs SReg_32:$vdst), - (ins VGPR_32:$src0, SCSrc_32:$src1), + (ins VS_32:$src0, SCSrc_32:$src1), "v_readlane_b32 $vdst, $src0, $src1" >; |
