diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstructions.td | 4 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/AMDGPU/vop1_vi.txt | 3 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/AMDGPU/vop2_vi.txt | 4 |
3 files changed, 7 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 88f1f0c8a8d..2d8651b25a3 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -1205,7 +1205,7 @@ let Uses = [EXEC] in { def V_READFIRSTLANE_B32 : VOP1 < 0x00000002, (outs SReg_32:$vdst), - (ins VGPR_32:$src0), + (ins VS_32:$src0), "v_readfirstlane_b32 $vdst, $src0", [] >; @@ -1579,7 +1579,7 @@ defm V_READLANE_B32 : VOP2SI_3VI_m < vop3 <0x001, 0x289>, "v_readlane_b32", (outs SReg_32:$vdst), - (ins VGPR_32:$src0, SCSrc_32:$src1), + (ins VS_32:$src0, SCSrc_32:$src1), "v_readlane_b32 $vdst, $src0, $src1" >; diff --git a/llvm/test/MC/Disassembler/AMDGPU/vop1_vi.txt b/llvm/test/MC/Disassembler/AMDGPU/vop1_vi.txt index b1bf4511722..70870068349 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/vop1_vi.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/vop1_vi.txt @@ -3,6 +3,9 @@ # VI: v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e] 0x00 0x6a 0x00 0x7e +# VI: v_readfirstlane_b32 s1, v2 ; encoding: [0x02,0x05,0x02,0x7e] +0x02 0x05 0x02 0x7e + # VI: v_fract_f32_e32 v1, v2 ; encoding: [0x02,0x37,0x02,0x7e] 0x02 0x37 0x02 0x7e diff --git a/llvm/test/MC/Disassembler/AMDGPU/vop2_vi.txt b/llvm/test/MC/Disassembler/AMDGPU/vop2_vi.txt index 277c27f5b92..c302c68c64e 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/vop2_vi.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/vop2_vi.txt @@ -1,7 +1,7 @@ # RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI -# FIXME: v_readlane_b32 s1, v2, s3 ; encoding: [0x01,0x00,0x89,0xd2,0x02,0x07,0x00,0x00] -#0x01 0x00 0x89 0xd2 0x02 0x07 0x00 0x00 +# VI: v_readlane_b32 s1, v2, s3 ; encoding: [0x01,0x00,0x89,0xd2,0x02,0x07,0x00,0x00] +0x01 0x00 0x89 0xd2 0x02 0x07 0x00 0x00 # VI: v_writelane_b32 v1, s2, s3 ; encoding: [0x01,0x00,0x8a,0xd2,0x02,0x06,0x00,0x00] 0x01 0x00 0x8a 0xd2 0x02 0x06 0x00 0x00 |
