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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-10-06 16:20:41 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-10-06 16:20:41 +0000 |
| commit | 6bc43d8627ca44465e7ce261a0828b70d3460e13 (patch) | |
| tree | 255944724c060d2eef50f0ccf04df7546aca245c /llvm/lib/Target/AMDGPU/SOPInstructions.td | |
| parent | d391d6f1c32d7316cb7fa8cfa4e039f94133ccbe (diff) | |
| download | bcm5719-llvm-6bc43d8627ca44465e7ce261a0828b70d3460e13.tar.gz bcm5719-llvm-6bc43d8627ca44465e7ce261a0828b70d3460e13.zip | |
BranchRelaxation: Support expanding unconditional branches
AMDGPU needs to expand unconditional branches in a new
block with an indirect branch.
llvm-svn: 283464
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SOPInstructions.td')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SOPInstructions.td | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td index d31002b999a..404ee4260aa 100644 --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -25,6 +25,7 @@ class SOP1_Pseudo <string opName, dag outs, dag ins, let SALU = 1; let SOP1 = 1; let SchedRW = [WriteSALU]; + let Size = 4; let UseNamedOperandTable = 1; string Mnemonic = opName; @@ -41,6 +42,7 @@ class SOP1_Real<bits<8> op, SOP1_Pseudo ps> : let isPseudo = 0; let isCodeGenOnly = 0; + let Size = 4; // copy relevant pseudo op flags let SubtargetPredicate = ps.SubtargetPredicate; |
