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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-10-28 23:00:38 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-10-28 23:00:38 +0000 |
| commit | 4e9c1e3a793b6120ac6a0f8075ea26d0762c5888 (patch) | |
| tree | 1bd70b74b1335bc1a945de6f2162247ea07f1895 /llvm/lib/Target/AMDGPU/SOPInstructions.td | |
| parent | 3cd37d0aeb6d57d89bed1df8b185fb17f5cc7d48 (diff) | |
| download | bcm5719-llvm-4e9c1e3a793b6120ac6a0f8075ea26d0762c5888.tar.gz bcm5719-llvm-4e9c1e3a793b6120ac6a0f8075ea26d0762c5888.zip | |
AMDGPU: Fix instruction flags for s_endpgm
Set isReturn, remove hasSideEffects. Also remove
hasCtrlDep, I'm not really sure what that does.
llvm-svn: 285476
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SOPInstructions.td')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SOPInstructions.td | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td index 7056b41c695..0d376b97b5f 100644 --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -743,8 +743,7 @@ def S_ENDPGM : SOPP <0x00000001, (ins), "s_endpgm", [(AMDGPUendpgm)]> { let simm16 = 0; let isBarrier = 1; - let hasCtrlDep = 1; - let hasSideEffects = 1; + let isReturn = 1; } let isBranch = 1, SchedRW = [WriteBranch] in { |
