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| author | Tim Corringham <tcorring@amd.com> | 2017-05-25 14:04:14 +0000 |
|---|---|---|
| committer | Tim Corringham <tcorring@amd.com> | 2017-05-25 14:04:14 +0000 |
| commit | 32d0d3867949e1c0c00e76f440a2b67f8b09c7b0 (patch) | |
| tree | 92bab1a295f4891a6d3c659d64a3c89defe85788 /llvm/lib/Target/AMDGPU/SOPInstructions.td | |
| parent | 7bf27f03f2cbd97bfff141efb34c6dc0db693f2f (diff) | |
| download | bcm5719-llvm-32d0d3867949e1c0c00e76f440a2b67f8b09c7b0.tar.gz bcm5719-llvm-32d0d3867949e1c0c00e76f440a2b67f8b09c7b0.zip | |
[AMDGPU] add intrinsic for s_getpc
Summary: The s_getpc instruction is exposed as intrinsic llvm.amdgcn.s.getpc.
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye
Differential Revision: https://reviews.llvm.org/D32862
llvm-svn: 303859
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SOPInstructions.td')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SOPInstructions.td | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td index f2d8b6f7b7a..ec29a66c8bb 100644 --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -184,7 +184,9 @@ def S_BITSET0_B32 : SOP1_32 <"s_bitset0_b32">; def S_BITSET0_B64 : SOP1_64_32 <"s_bitset0_b64">; def S_BITSET1_B32 : SOP1_32 <"s_bitset1_b32">; def S_BITSET1_B64 : SOP1_64_32 <"s_bitset1_b64">; -def S_GETPC_B64 : SOP1_64_0 <"s_getpc_b64">; +def S_GETPC_B64 : SOP1_64_0 <"s_getpc_b64", + [(set i64:$sdst, (int_amdgcn_s_getpc))] +>; let isTerminator = 1, isBarrier = 1, SchedRW = [WriteBranch] in { |
