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| author | Tom Stellard <thomas.stellard@amd.com> | 2016-11-03 17:13:50 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2016-11-03 17:13:50 +0000 |
| commit | 2b3379cdffaa5d2af96abf0489f9755149be1f8e (patch) | |
| tree | 95c48ec395af390718e2900e4eed4bbefd0d257a /llvm/lib/Target/AMDGPU/SOPInstructions.td | |
| parent | 40c15abe5fa31468f3ccc5c4439d29bb5e2e8c71 (diff) | |
| download | bcm5719-llvm-2b3379cdffaa5d2af96abf0489f9755149be1f8e.tar.gz bcm5719-llvm-2b3379cdffaa5d2af96abf0489f9755149be1f8e.zip | |
AMDGPU: Add VI i16 support
Patch By: Wei Ding
Differential Revision: https://reviews.llvm.org/D18049
llvm-svn: 285939
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SOPInstructions.td')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SOPInstructions.td | 37 |
1 files changed, 36 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td index e38a11db9ac..2486fbf3edf 100644 --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -879,7 +879,7 @@ def : Pat < (i64 (ctpop i64:$src)), (i64 (REG_SEQUENCE SReg_64, (i32 (COPY_TO_REGCLASS (S_BCNT1_I32_B64 $src), SReg_32)), sub0, - (S_MOV_B32 0), sub1)) + (S_MOV_B32 (i32 0)), sub1)) >; def : Pat < @@ -887,6 +887,18 @@ def : Pat < (S_ABS_I32 $x) >; +def : Pat < + (i16 imm:$imm), + (S_MOV_B32 imm:$imm) +>; + +// Same as a 32-bit inreg +def : Pat< + (i32 (sext i16:$src)), + (S_SEXT_I32_I16 $src) +>; + + //===----------------------------------------------------------------------===// // SOP2 Patterns //===----------------------------------------------------------------------===// @@ -898,6 +910,29 @@ def : Pat < (S_ADD_U32 $src0, $src1) >; +// FIXME: We need to use COPY_TO_REGCLASS to work-around the fact that +// REG_SEQUENCE patterns don't support instructions with multiple +// outputs. +def : Pat< + (i64 (zext i16:$src)), + (REG_SEQUENCE SReg_64, + (i32 (COPY_TO_REGCLASS (S_AND_B32 $src, (S_MOV_B32 (i32 0xffff))), SGPR_32)), sub0, + (S_MOV_B32 (i32 0)), sub1) +>; + +def : Pat < + (i64 (sext i16:$src)), + (REG_SEQUENCE SReg_64, (i32 (S_SEXT_I32_I16 $src)), sub0, + (i32 (COPY_TO_REGCLASS (S_ASHR_I32 (i32 (S_SEXT_I32_I16 $src)), (S_MOV_B32 (i32 31))), SGPR_32)), sub1) +>; + +def : Pat< + (i32 (zext i16:$src)), + (S_AND_B32 (S_MOV_B32 (i32 0xffff)), $src) +>; + + + //===----------------------------------------------------------------------===// // SOPP Patterns //===----------------------------------------------------------------------===// |
