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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2017-06-19 23:17:36 +0000 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2017-06-19 23:17:36 +0000 |
| commit | 50c2f251f54935471464e2d1850858b633f46c38 (patch) | |
| tree | 660fbbecbba128fe2ec75568e37676bb5c5bba8b /llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | |
| parent | 9565c75b29826f48a0923e401a885f391b6c1dc3 (diff) | |
| download | bcm5719-llvm-50c2f251f54935471464e2d1850858b633f46c38.tar.gz bcm5719-llvm-50c2f251f54935471464e2d1850858b633f46c38.zip | |
[AMDGPU] Add infer address spaces pass before SROA
It adds it for the target after inlining but before SROA where
we can get most out of it.
Differential Revision: https://reviews.llvm.org/D34366
llvm-svn: 305759
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp')
0 files changed, 0 insertions, 0 deletions
