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author | Geoff Berry <gberry@codeaurora.org> | 2018-01-29 18:47:48 +0000 |
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committer | Geoff Berry <gberry@codeaurora.org> | 2018-01-29 18:47:48 +0000 |
commit | d37dc77b6e52d46f2388070f2fd530424b49a8cd (patch) | |
tree | fe09801732f33a3e4f05668d1eba70de4f02a05a /llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp | |
parent | d5f76ad37fb235c684d551251eb8c0e204bde134 (diff) | |
download | bcm5719-llvm-d37dc77b6e52d46f2388070f2fd530424b49a8cd.tar.gz bcm5719-llvm-d37dc77b6e52d46f2388070f2fd530424b49a8cd.zip |
[AMDGPU][X86][Mips] Make sure renamable bit not set for reserved regs
Summary:
Fix a few places that were modifying code after register
allocation to set the renamable bit correctly to avoid failing the
validation added in D42449.
llvm-svn: 323675
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp')
-rw-r--r-- | llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp index 2dc6f2702b3..e77c98a72cf 100644 --- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp +++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp @@ -246,6 +246,7 @@ bool SIOptimizeExecMasking::runOnMachineFunction(MachineFunction &MF) { DEBUG(dbgs() << "Fold exec copy: " << *PrepareExecInst); PrepareExecInst->getOperand(0).setReg(AMDGPU::EXEC); + PrepareExecInst->getOperand(0).setIsRenamable(false); DEBUG(dbgs() << "into: " << *PrepareExecInst << '\n'); @@ -352,7 +353,8 @@ bool SIOptimizeExecMasking::runOnMachineFunction(MachineFunction &MF) { for (MachineInstr *OtherInst : OtherUseInsts) { OtherInst->substituteRegister(CopyToExec, AMDGPU::EXEC, - AMDGPU::NoSubRegister, *TRI); + AMDGPU::NoSubRegister, *TRI, + /*ClearIsRenamable=*/true); } } |