From d37dc77b6e52d46f2388070f2fd530424b49a8cd Mon Sep 17 00:00:00 2001 From: Geoff Berry Date: Mon, 29 Jan 2018 18:47:48 +0000 Subject: [AMDGPU][X86][Mips] Make sure renamable bit not set for reserved regs Summary: Fix a few places that were modifying code after register allocation to set the renamable bit correctly to avoid failing the validation added in D42449. llvm-svn: 323675 --- llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp') diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp index 2dc6f2702b3..e77c98a72cf 100644 --- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp +++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp @@ -246,6 +246,7 @@ bool SIOptimizeExecMasking::runOnMachineFunction(MachineFunction &MF) { DEBUG(dbgs() << "Fold exec copy: " << *PrepareExecInst); PrepareExecInst->getOperand(0).setReg(AMDGPU::EXEC); + PrepareExecInst->getOperand(0).setIsRenamable(false); DEBUG(dbgs() << "into: " << *PrepareExecInst << '\n'); @@ -352,7 +353,8 @@ bool SIOptimizeExecMasking::runOnMachineFunction(MachineFunction &MF) { for (MachineInstr *OtherInst : OtherUseInsts) { OtherInst->substituteRegister(CopyToExec, AMDGPU::EXEC, - AMDGPU::NoSubRegister, *TRI); + AMDGPU::NoSubRegister, *TRI, + /*ClearIsRenamable=*/true); } } -- cgit v1.2.3