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authorMatt Arsenault <Matthew.Arsenault@amd.com>2017-03-17 21:36:28 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2017-03-17 21:36:28 +0000
commit59ece95f6c2e814062e31f3b065bfd492b597862 (patch)
tree55a0ed18b743b439671585b67acf622a71b1dd09 /llvm/lib/Target/AMDGPU/SIInstrInfo.h
parentf790f788b61cf8b0f15f9d95a23e474969c41c32 (diff)
downloadbcm5719-llvm-59ece95f6c2e814062e31f3b065bfd492b597862.tar.gz
bcm5719-llvm-59ece95f6c2e814062e31f3b065bfd492b597862.zip
AMDGPU: Fix broken condition in hazard recognizer
Fixes bug 32248. llvm-svn: 298125
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIInstrInfo.h')
-rw-r--r--llvm/lib/Target/AMDGPU/SIInstrInfo.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 6723105c07e..b201c5037dc 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -451,6 +451,14 @@ public:
return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
}
+ static bool isVINTRP(const MachineInstr &MI) {
+ return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
+ }
+
+ bool isVINTRP(uint16_t Opcode) const {
+ return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
+ }
+
static bool isScalarUnit(const MachineInstr &MI) {
return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD);
}
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