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authorMatt Arsenault <Matthew.Arsenault@amd.com>2017-09-13 23:47:01 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2017-09-13 23:47:01 +0000
commitecb43ef1bca8bfd8e27b3c65451eee11ef5898f3 (patch)
treefb897031081eaf568df542322110f7e0479509ef /llvm/lib
parentcc40ef859ad671f20fa3f82ab70c4795c925bb3b (diff)
downloadbcm5719-llvm-ecb43ef1bca8bfd8e27b3c65451eee11ef5898f3.tar.gz
bcm5719-llvm-ecb43ef1bca8bfd8e27b3c65451eee11ef5898f3.zip
AMDGPU: Don't spill SP reg like a normal CSR
llvm-svn: 313217
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/AMDGPU/SIFrameLowering.cpp9
-rw-r--r--llvm/lib/Target/AMDGPU/SIFrameLowering.h3
-rw-r--r--llvm/lib/Target/AMDGPU/SIInstrInfo.cpp4
3 files changed, 16 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
index 2ecf32c6ffe..ff6fed88e37 100644
--- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -594,6 +594,15 @@ void SIFrameLowering::processFunctionBeforeFrameFinalized(
}
}
+void SIFrameLowering::determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
+ RegScavenger *RS) const {
+ TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
+ const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
+
+ // The SP is specifically managed and we don't want extra spills of it.
+ SavedRegs.reset(MFI->getStackPtrOffsetReg());
+}
+
MachineBasicBlock::iterator SIFrameLowering::eliminateCallFramePseudoInstr(
MachineFunction &MF,
MachineBasicBlock &MBB,
diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.h b/llvm/lib/Target/AMDGPU/SIFrameLowering.h
index c23969d711b..cc1c85ff6bf 100644
--- a/llvm/lib/Target/AMDGPU/SIFrameLowering.h
+++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.h
@@ -35,6 +35,9 @@ public:
int getFrameIndexReference(const MachineFunction &MF, int FI,
unsigned &FrameReg) const override;
+ void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
+ RegScavenger *RS = nullptr) const override;
+
void processFunctionBeforeFrameFinalized(
MachineFunction &MF,
RegScavenger *RS = nullptr) const override;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 2279afaf89e..73eb3a3b5f6 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -818,6 +818,10 @@ void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineFrameInfo &FrameInfo = MF->getFrameInfo();
DebugLoc DL = MBB.findDebugLoc(MI);
+ assert(SrcReg != MFI->getStackPtrOffsetReg() &&
+ SrcReg != MFI->getFrameOffsetReg() &&
+ SrcReg != MFI->getScratchWaveOffsetReg());
+
unsigned Size = FrameInfo.getObjectSize(FrameIndex);
unsigned Align = FrameInfo.getObjectAlignment(FrameIndex);
MachinePointerInfo PtrInfo
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