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| author | Tom Stellard <thomas.stellard@amd.com> | 2016-05-02 17:39:06 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2016-05-02 17:39:06 +0000 |
| commit | 1f520e5c98a0fbeaa1347ea1e58a3f58721ae98c (patch) | |
| tree | 8b8ede37f32568e74beb048b09157f87bef3c498 /llvm/lib/Target/AMDGPU/SIInsertWaits.cpp | |
| parent | 119d3d80cbb53ff601f5bf56affb464d3b5f55ea (diff) | |
| download | bcm5719-llvm-1f520e5c98a0fbeaa1347ea1e58a3f58721ae98c.tar.gz bcm5719-llvm-1f520e5c98a0fbeaa1347ea1e58a3f58721ae98c.zip | |
AMDGPU/SI: Use the hazard recognizer to break SMEM soft clauses
Summary:
Add support for detecting hazards in SMEM soft clauses, so that we only
break the clauses when necessary, either by adding s_nop or re-ordering
other alu instructions.
Reviewers: arsenm
Subscribers: arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D18870
llvm-svn: 268260
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIInsertWaits.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInsertWaits.cpp | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp index 75adb2b767f..abc9c4d6184 100644 --- a/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp +++ b/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp @@ -314,8 +314,7 @@ void SIInsertWaits::pushInstruction(MachineBasicBlock &MBB, // and destination registers don't overlap, e.g. this is illegal: // r0 = load r2 // r2 = load r0 - if ((LastOpcodeType == SMEM && TII->isSMRD(*I)) || - (LastOpcodeType == VMEM && Increment.Named.VM)) { + if (LastOpcodeType == VMEM && Increment.Named.VM) { // Insert a NOP to break the clause. BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_NOP)) .addImm(0); |
