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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-09-18 02:34:54 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-09-18 02:34:54 +0000 |
| commit | ebf46143eaf7fa3ad956baf8cc876cbe2c6ae306 (patch) | |
| tree | 6f5f635699a2260849cffa397f4052c2609f8b14 /llvm/lib/Target/AMDGPU/SIISelLowering.cpp | |
| parent | c64079859767f30319bd3ceb93e36f35e2dc0b17 (diff) | |
| download | bcm5719-llvm-ebf46143eaf7fa3ad956baf8cc876cbe2c6ae306.tar.gz bcm5719-llvm-ebf46143eaf7fa3ad956baf8cc876cbe2c6ae306.zip | |
AMDGPU: Don't form fmed3 if it will require materialization
If there is a single use constant, it can be folded into the
min/max, but not into med3.
llvm-svn: 342443
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 47217a06d48..3de6a546a4f 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -7733,8 +7733,15 @@ SDValue SITargetLowering::performFPMed3ImmCombine(SelectionDAG &DAG, if (!DAG.isKnownNeverSNaN(Var)) return SDValue(); - return DAG.getNode(AMDGPUISD::FMED3, SL, K0->getValueType(0), - Var, SDValue(K0, 0), SDValue(K1, 0)); + const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); + + if ((!K0->hasOneUse() || + TII->isInlineConstant(K0->getValueAPF().bitcastToAPInt())) && + (!K1->hasOneUse() || + TII->isInlineConstant(K1->getValueAPF().bitcastToAPInt()))) { + return DAG.getNode(AMDGPUISD::FMED3, SL, K0->getValueType(0), + Var, SDValue(K0, 0), SDValue(K1, 0)); + } } return SDValue(); |
