From ebf46143eaf7fa3ad956baf8cc876cbe2c6ae306 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 18 Sep 2018 02:34:54 +0000 Subject: AMDGPU: Don't form fmed3 if it will require materialization If there is a single use constant, it can be folded into the min/max, but not into med3. llvm-svn: 342443 --- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.cpp') diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 47217a06d48..3de6a546a4f 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -7733,8 +7733,15 @@ SDValue SITargetLowering::performFPMed3ImmCombine(SelectionDAG &DAG, if (!DAG.isKnownNeverSNaN(Var)) return SDValue(); - return DAG.getNode(AMDGPUISD::FMED3, SL, K0->getValueType(0), - Var, SDValue(K0, 0), SDValue(K1, 0)); + const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); + + if ((!K0->hasOneUse() || + TII->isInlineConstant(K0->getValueAPF().bitcastToAPInt())) && + (!K1->hasOneUse() || + TII->isInlineConstant(K1->getValueAPF().bitcastToAPInt()))) { + return DAG.getNode(AMDGPUISD::FMED3, SL, K0->getValueType(0), + Var, SDValue(K0, 0), SDValue(K1, 0)); + } } return SDValue(); -- cgit v1.2.3