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authorMatt Arsenault <Matthew.Arsenault@amd.com>2018-12-07 17:46:16 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2018-12-07 17:46:16 +0000
commitaa9bcd56b13f07468a1de0b46d374b82fb8a1f5e (patch)
tree7a8073fab1f4e3412a89bf32cb991d0062bd8700 /llvm/lib
parent30388d6485e8d2afd48cabffc64e921d0585e8ba (diff)
downloadbcm5719-llvm-aa9bcd56b13f07468a1de0b46d374b82fb8a1f5e.tar.gz
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AMDGPU: Remove llvm.AMDGPU.kill
This is the last of the old AMDGPU intrinsics. llvm-svn: 348615
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPU.td1
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUIntrinsicInfo.cpp4
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUIntrinsicInfo.h2
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUIntrinsics.td16
-rw-r--r--llvm/lib/Target/AMDGPU/SIISelLowering.cpp17
5 files changed, 5 insertions, 35 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 8530be9269c..0aacedf24e3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -764,7 +764,6 @@ def EnableLateCFGStructurize : Predicate<
include "SISchedule.td"
include "GCNProcessors.td"
include "AMDGPUInstrInfo.td"
-include "AMDGPUIntrinsics.td"
include "SIIntrinsics.td"
include "AMDGPURegisterInfo.td"
include "AMDGPURegisterBanks.td"
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUIntrinsicInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUIntrinsicInfo.cpp
index 896e2055cf6..02108ca3ddd 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUIntrinsicInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUIntrinsicInfo.cpp
@@ -40,7 +40,7 @@ StringRef AMDGPUIntrinsicInfo::getName(unsigned IntrID,
if (IntrID < Intrinsic::num_intrinsics)
return StringRef();
- assert(IntrID < AMDGPUIntrinsic::num_AMDGPU_intrinsics &&
+ assert(IntrID < SIIntrinsic::num_AMDGPU_intrinsics &&
"Invalid intrinsic ID");
return IntrinsicNameTable[IntrID - Intrinsic::num_intrinsics];
@@ -91,7 +91,7 @@ Function *AMDGPUIntrinsicInfo::getDeclaration(Module *M, unsigned IntrID,
= cast<Function>(M->getOrInsertFunction(getName(IntrID, Tys), FTy));
AttributeList AS =
- getAttributes(M->getContext(), static_cast<AMDGPUIntrinsic::ID>(IntrID));
+ getAttributes(M->getContext(), static_cast<SIIntrinsic::ID>(IntrID));
F->setAttributes(AS);
return F;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUIntrinsicInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUIntrinsicInfo.h
index ef42f9a319a..a1a094dded2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUIntrinsicInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUIntrinsicInfo.h
@@ -20,7 +20,7 @@
namespace llvm {
class TargetMachine;
-namespace AMDGPUIntrinsic {
+namespace SIIntrinsic {
enum ID {
last_non_AMDGPU_intrinsic = Intrinsic::num_intrinsics - 1,
#define GET_INTRINSIC_ENUM_VALUES
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUIntrinsics.td b/llvm/lib/Target/AMDGPU/AMDGPUIntrinsics.td
deleted file mode 100644
index 230a0462850..00000000000
--- a/llvm/lib/Target/AMDGPU/AMDGPUIntrinsics.td
+++ /dev/null
@@ -1,16 +0,0 @@
-//===-- AMDGPUIntrinsics.td - Common intrinsics -*- tablegen -*-----------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines intrinsics that are used by all hw codegen targets.
-//
-//===----------------------------------------------------------------------===//
-
-let TargetPrefix = "AMDGPU", isTarget = 1 in {
- def int_AMDGPU_kill : Intrinsic<[], [llvm_float_ty], []>;
-}
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index fd4b1f361cd..ca9866f441c 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5065,7 +5065,7 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
SDLoc(DAG.getEntryNode()),
MFI->getArgInfo().WorkItemIDZ);
- case AMDGPUIntrinsic::SI_load_const: {
+ case SIIntrinsic::SI_load_const: {
SDValue Load =
lowerSBuffer(MVT::i32, DL, Op.getOperand(1), Op.getOperand(2),
DAG.getTargetConstant(0, DL, MVT::i1), DAG);
@@ -5808,19 +5808,6 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
return DAG.getNode(AMDGPUISD::INIT_EXEC_FROM_INPUT, DL, MVT::Other, Chain,
Op.getOperand(2), Op.getOperand(3));
}
- case AMDGPUIntrinsic::AMDGPU_kill: {
- SDValue Src = Op.getOperand(2);
- if (const ConstantFPSDNode *K = dyn_cast<ConstantFPSDNode>(Src)) {
- if (!K->isNegative())
- return Chain;
-
- SDValue NegOne = DAG.getTargetConstant(FloatToBits(-1.0f), DL, MVT::i32);
- return DAG.getNode(AMDGPUISD::KILL, DL, MVT::Other, Chain, NegOne);
- }
-
- SDValue Cast = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Src);
- return DAG.getNode(AMDGPUISD::KILL, DL, MVT::Other, Chain, Cast);
- }
case Intrinsic::amdgcn_s_barrier: {
if (getTargetMachine().getOptLevel() > CodeGenOpt::None) {
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
@@ -5831,7 +5818,7 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
}
return SDValue();
};
- case AMDGPUIntrinsic::SI_tbuffer_store: {
+ case SIIntrinsic::SI_tbuffer_store: {
// Extract vindex and voffset from vaddr as appropriate
const ConstantSDNode *OffEn = cast<ConstantSDNode>(Op.getOperand(10));
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