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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-09-21 16:27:22 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-09-21 16:27:22 +0000 |
| commit | 85441dd7244939be233724a49d00a83b54ae7c2e (patch) | |
| tree | cdbe21aa40f4ca3db09e62c1f2da37adb92e4567 /llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | |
| parent | b1c39429d97ad107b6798e77765543da3258bc06 (diff) | |
| download | bcm5719-llvm-85441dd7244939be233724a49d00a83b54ae7c2e.tar.gz bcm5719-llvm-85441dd7244939be233724a49d00a83b54ae7c2e.zip | |
AMDGPU: Move copy handling under switch like other instructions
llvm-svn: 248172
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp index 1cf520d360e..55899b729c3 100644 --- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp +++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp @@ -214,13 +214,18 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I) { MachineInstr &MI = *I; - if (MI.getOpcode() == AMDGPU::COPY && isVGPRToSGPRCopy(MI, TRI, MRI)) { - DEBUG(dbgs() << "Fixing VGPR -> SGPR copy: " << MI); - TII->moveToVALU(MI); - } switch (MI.getOpcode()) { - default: continue; + default: + continue; + case AMDGPU::COPY: { + if (isVGPRToSGPRCopy(MI, TRI, MRI)) { + DEBUG(dbgs() << "Fixing VGPR -> SGPR copy: " << MI); + TII->moveToVALU(MI); + } + + break; + } case AMDGPU::PHI: { DEBUG(dbgs() << "Fixing PHI: " << MI); |
