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| author | Artem Tamazov <artem.tamazov@amd.com> | 2016-04-27 16:20:23 +0000 |
|---|---|---|
| committer | Artem Tamazov <artem.tamazov@amd.com> | 2016-04-27 16:20:23 +0000 |
| commit | 3896f8f83d236c543945b0bcee0d341dbfb6c2ab (patch) | |
| tree | d3561e7091aa9d7c6ad0910abbc9b32d10ee181c /llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h | |
| parent | 0336cc05e718cd394cfd22ab519f9a9a4c998b08 (diff) | |
| download | bcm5719-llvm-3896f8f83d236c543945b0bcee0d341dbfb6c2ab.tar.gz bcm5719-llvm-3896f8f83d236c543945b0bcee0d341dbfb6c2ab.zip | |
[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for SMRD.
Added support of TTMP quads.
Reworked M0 exclusion machinery for SMRD and similar instructions
to enable usage of TTMP registers in those instructions as destinations.
Tests added.
Differential Revision: http://reviews.llvm.org/D19342
llvm-svn: 267733
Diffstat (limited to 'llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h index f1ba30e7bf5..680ed3068a1 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h @@ -64,6 +64,7 @@ namespace llvm { MCOperand decodeOperand_SGPR_32(unsigned Val) const; MCOperand decodeOperand_SReg_32(unsigned Val) const; + MCOperand decodeOperand_SReg_32_XM0(unsigned Val) const; MCOperand decodeOperand_SReg_64(unsigned Val) const; MCOperand decodeOperand_SReg_128(unsigned Val) const; MCOperand decodeOperand_SReg_256(unsigned Val) const; |
