diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-06-20 21:11:42 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-06-20 21:11:42 +0000 |
| commit | 740322f1eb9d9e8777f7bf2945038bd8d6b7bdf4 (patch) | |
| tree | fe0f9dbf131a3821197f76181ff456be37ac71ec /llvm/lib/Target/AMDGPU/DSInstructions.td | |
| parent | d0b11698cdf87981ae6c94c7b9d75b190baabe8c (diff) | |
| download | bcm5719-llvm-740322f1eb9d9e8777f7bf2945038bd8d6b7bdf4.tar.gz bcm5719-llvm-740322f1eb9d9e8777f7bf2945038bd8d6b7bdf4.zip | |
AMDGPU: Add intrinsics for DS GWS semaphore instructions
llvm-svn: 363983
Diffstat (limited to 'llvm/lib/Target/AMDGPU/DSInstructions.td')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/DSInstructions.td | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td index 0ef5d79d66a..7890fa1502e 100644 --- a/llvm/lib/Target/AMDGPU/DSInstructions.td +++ b/llvm/lib/Target/AMDGPU/DSInstructions.td @@ -557,7 +557,9 @@ let SubtargetPredicate = isGFX7Plus in { defm DS_WRAP_RTN_B32 : DS_1A2D_RET_mc<"ds_wrap_rtn_b32", VGPR_32>; defm DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET_mc<"ds_condxchg32_rtn_b64", VReg_64>; +let isConvergent = 1, usesCustomInserter = 1 in { def DS_GWS_SEMA_RELEASE_ALL : DS_GWS_0D<"ds_gws_sema_release_all">; +} let mayStore = 0 in { defm DS_READ_B96 : DS_1A_RET_mc<"ds_read_b96", VReg_96>; |
