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authorFlorian Hahn <florian.hahn@arm.com>2017-07-07 10:15:49 +0000
committerFlorian Hahn <florian.hahn@arm.com>2017-07-07 10:15:49 +0000
commite3666ec9d6fc5debb641b073d16f1940242bf6cd (patch)
tree58ef6c261853587daf5fea9cbc644b48488a8a76 /llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
parent91dafe09b05524d7b102b00a1e82dacbd68f0af7 (diff)
downloadbcm5719-llvm-e3666ec9d6fc5debb641b073d16f1940242bf6cd.tar.gz
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[AArch64] Use 16 bytes as preferred function alignment on Cortex-A72.
Summary: This change gives a 0.34% speed on execution time, a 0.61% improvement in benchmark scores and a 0.57% increase in binary size on a Cortex-A72. These numbers are the geomean results on a wide range of benchmarks from the test-suite, SPEC2000, SPEC2006 and a range of proprietary suites. The software optimization guide for the Cortex-A72 recommends 16 byte branch alignment. Reviewers: t.p.northover, kristof.beyls, rengolin, sbaranga, mcrosier, javed.absar Reviewed By: kristof.beyls Subscribers: llvm-commits, aemerson Differential Revision: https://reviews.llvm.org/D34961 llvm-svn: 307380
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp')
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