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| author | Wei Ding <wei.ding2@amd.com> | 2017-10-12 19:37:14 +0000 |
|---|---|---|
| committer | Wei Ding <wei.ding2@amd.com> | 2017-10-12 19:37:14 +0000 |
| commit | 5676acad9e0b530aae507e0b1482cc87c949b762 (patch) | |
| tree | ff0f17fe3a809f5c402d4e0c61de1ec73c5d75ca /llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | |
| parent | ca05b6fb798f2eed32756c7dfc8886411609bdd8 (diff) | |
| download | bcm5719-llvm-5676acad9e0b530aae507e0b1482cc87c949b762.tar.gz bcm5719-llvm-5676acad9e0b530aae507e0b1482cc87c949b762.zip | |
Implement custom lowering for ISD::CTTZ_ZERO_UNDEF and ISD::CTTZ.
Differential Revision: http://reviews.llvm.org/D37348
llvm-svn: 315610
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h index a2af7c3d790..3b0304ab16a 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h @@ -32,7 +32,7 @@ private: /// legalized from a smaller type VT. Need to match pre-legalized type because /// the generic legalization inserts the add/sub between the select and /// compare. - SDValue getFFBH_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL) const; + SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const; public: static bool isOrEquivalentToAdd(SelectionDAG &DAG, SDValue Op); @@ -57,7 +57,7 @@ protected: SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const; SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const; @@ -88,7 +88,7 @@ protected: SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const; - SDValue performCtlzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS, + SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS, SDValue RHS, DAGCombinerInfo &DCI) const; SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const; @@ -371,6 +371,7 @@ enum NodeType : unsigned { BFM, // Insert a range of bits into a 32-bit word. FFBH_U32, // ctlz with -1 if input is zero. FFBH_I32, + FFBL_B32, // cttz with -1 if input is zero. MUL_U24, MUL_I24, MULHI_U24, |
