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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-01-18 22:09:04 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-01-18 22:09:04 +0000 |
| commit | 33e3ecee0c44169f11d1fc4472250c1346e68a4e (patch) | |
| tree | aefe8d1832cb203a53914cc47e3ecd8bb4bf5432 /llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | |
| parent | 6e3a45193aa927de0d4a677594f74c31cfc26727 (diff) | |
| download | bcm5719-llvm-33e3ecee0c44169f11d1fc4472250c1346e68a4e.tar.gz bcm5719-llvm-33e3ecee0c44169f11d1fc4472250c1346e68a4e.zip | |
AMDGPU: Reduce 64-bit SRAs
llvm-svn: 258096
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h index fa52c66f5a7..eae62b7642e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h @@ -87,6 +87,8 @@ protected: /// Return 64-bit value Op as two 32-bit integers. std::pair<SDValue, SDValue> split64BitValue(SDValue Op, SelectionDAG &DAG) const; + SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const; + SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const; /// \brief Split a vector load into a scalar load of each component. SDValue ScalarizeVectorLoad(SDValue Op, SelectionDAG &DAG) const; |
