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| author | Tim Corringham <tcorring@amd.com> | 2019-01-28 13:48:59 +0000 |
|---|---|---|
| committer | Tim Corringham <tcorring@amd.com> | 2019-01-28 13:48:59 +0000 |
| commit | 824ca3f3dd8584db7a015a550be5ee512d8e362f (patch) | |
| tree | 6777ac02abf444cfe04c2c4ec86a37824fccb88f /llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | |
| parent | 575c0855c04f2549025e4a8b4df9e58c80009146 (diff) | |
| download | bcm5719-llvm-824ca3f3dd8584db7a015a550be5ee512d8e362f.tar.gz bcm5719-llvm-824ca3f3dd8584db7a015a550be5ee512d8e362f.zip | |
[AMDGPU] Add intrinsics for 16 bit interpolation
Summary:
Added the intrinsics llvm.amdgcn.interp.p1.f16() and
llvm.amdgcn.interp.p2.f16() and related LIT test.
The p1 intrinsic generates code appropriate for both 16 and 32
bank LDS.
Reviewers: #amdgpu, dstuttard, arsenm, tpr
Reviewed By: #amdgpu, arsenm
Subscribers: jvesely, mgorny, arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D46754
llvm-svn: 352357
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index f170bc53521..a15b2b99220 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -4183,6 +4183,9 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const { NODE_NAME_CASE(INTERP_MOV) NODE_NAME_CASE(INTERP_P1) NODE_NAME_CASE(INTERP_P2) + NODE_NAME_CASE(INTERP_P1LL_F16) + NODE_NAME_CASE(INTERP_P1LV_F16) + NODE_NAME_CASE(INTERP_P2_F16) NODE_NAME_CASE(STORE_MSKOR) NODE_NAME_CASE(LOAD_CONSTANT) NODE_NAME_CASE(TBUFFER_STORE_FORMAT) |
