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| author | Wei Ding <wei.ding2@amd.com> | 2017-10-17 21:49:52 +0000 |
|---|---|---|
| committer | Wei Ding <wei.ding2@amd.com> | 2017-10-17 21:49:52 +0000 |
| commit | 7ab1f7a421474d10847e478e7dc954a6217fe3e9 (patch) | |
| tree | a2e25df9a37006884db9140d9b1a0bcb1bc54a6c /llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | |
| parent | a2f96b5bde85bf496c3b8c26335757592fdea937 (diff) | |
| download | bcm5719-llvm-7ab1f7a421474d10847e478e7dc954a6217fe3e9.tar.gz bcm5719-llvm-7ab1f7a421474d10847e478e7dc954a6217fe3e9.zip | |
AMDGPU : Fix an error for the llvm.cttz implementation.
Differential Revision: http://reviews.llvm.org/D39014
llvm-svn: 316037
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 09914e0397c..fe2c9337721 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -2208,9 +2208,8 @@ SDValue AMDGPUTargetLowering::LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) cons EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32); - SDValue ZeroOrOne = isCtlzOpc(Op.getOpcode()) ? Zero : One; SDValue HiOrLo = isCtlzOpc(Op.getOpcode()) ? Hi : Lo; - SDValue Hi0orLo0 = DAG.getSetCC(SL, SetCCVT, HiOrLo, ZeroOrOne, ISD::SETEQ); + SDValue Hi0orLo0 = DAG.getSetCC(SL, SetCCVT, HiOrLo, Zero, ISD::SETEQ); SDValue OprLo = DAG.getNode(ISDOpc, SL, MVT::i32, Lo); SDValue OprHi = DAG.getNode(ISDOpc, SL, MVT::i32, Hi); @@ -2233,7 +2232,7 @@ SDValue AMDGPUTargetLowering::LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) cons // FIXME: DAG combines turn what should be an s_and_b64 into a v_or_b32, // which we probably don't want. SDValue LoOrHi = isCtlzOpc(Op.getOpcode()) ? Lo : Hi; - SDValue Lo0OrHi0 = DAG.getSetCC(SL, SetCCVT, LoOrHi, ZeroOrOne, ISD::SETEQ); + SDValue Lo0OrHi0 = DAG.getSetCC(SL, SetCCVT, LoOrHi, Zero, ISD::SETEQ); SDValue SrcIsZero = DAG.getNode(ISD::AND, SL, SetCCVT, Lo0OrHi0, Hi0orLo0); // TODO: If i64 setcc is half rate, it can result in 1 fewer instruction |
