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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-10-13 20:18:59 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-10-13 20:18:59 +0000 |
| commit | 4d70754e3cf57d76647b62cecaa37fb06815566a (patch) | |
| tree | f7a15623b1d3e237b2f3cd259c7b5b4e451d68e5 /llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | |
| parent | 28b3aa3663a4c3ed0cf23625a04f5bec8ae90653 (diff) | |
| download | bcm5719-llvm-4d70754e3cf57d76647b62cecaa37fb06815566a.tar.gz bcm5719-llvm-4d70754e3cf57d76647b62cecaa37fb06815566a.zip | |
AMDGPU: Implement isFPExtFoldable
This helps match v_mad_mix* in some cases.
llvm-svn: 315744
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 6146c49a0f1..09914e0397c 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -827,6 +827,17 @@ bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { return isZExtFree(Val.getValueType(), VT2); } +// v_mad_mix* support a conversion from f16 to f32. +// +// There is only one special case when denormals are enabled we don't currently, +// where this is OK to use. +bool AMDGPUTargetLowering::isFPExtFoldable(unsigned Opcode, + EVT DestVT, EVT SrcVT) const { + return Opcode == ISD::FMAD && Subtarget->hasMadMixInsts() && + DestVT.getScalarType() == MVT::f32 && !Subtarget->hasFP32Denormals() && + SrcVT.getScalarType() == MVT::f16; +} + bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const { // There aren't really 64-bit registers, but pairs of 32-bit ones and only a // limited number of native 64-bit operations. Shrinking an operation to fit |
