AMDGPU: Fold fneg into fp_round

llvm-svn: 291778

1 files changed, 18 insertions, 2 deletions

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 043f613b96c..2b6edba9f0b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -2903,7 +2903,7 @@ SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,
     SDValue CvtSrc = N0.getOperand(0);
     if (CvtSrc.getOpcode() == ISD::FNEG) {
       // (fneg (fp_extend (fneg x))) -> (fp_extend x)
-      return DAG.getNode(ISD::FP_EXTEND, SL, VT, CvtSrc.getOperand(0));
+      return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0));
     }
 
     if (!N0.hasOneUse())
@@ -2911,7 +2911,23 @@ SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,
 
     // (fneg (fp_extend x)) -> (fp_extend (fneg x))
     SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);
-    return DAG.getNode(ISD::FP_EXTEND, SL, VT, Neg);
+    return DAG.getNode(Opc, SL, VT, Neg);
+  }
+  case ISD::FP_ROUND: {
+    SDValue CvtSrc = N0.getOperand(0);
+
+    if (CvtSrc.getOpcode() == ISD::FNEG) {
+      // (fneg (fp_round (fneg x))) -> (fp_round x)
+      return DAG.getNode(ISD::FP_ROUND, SL, VT,
+                         CvtSrc.getOperand(0), N0.getOperand(1));
+    }
+
+    if (!N0.hasOneUse())
+      return SDValue();
+
+    // (fneg (fp_round x)) -> (fp_round (fneg x))
+    SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);
+    return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1));
   }
   default:
     return SDValue();