Revert "AMDGPU: Add VI i16 support"

This reverts commit r285939 and r285948.  These broke some conformance tests.

llvm-svn: 285995

1 files changed, 3 insertions, 24 deletions

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 118f8fabb7d..d7108416ccc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -586,32 +586,19 @@ bool AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources(EVT VecVT) const
 
 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
   // Truncate is just accessing a subregister.
-
-  unsigned SrcSize = Source.getSizeInBits();
-  unsigned DestSize = Dest.getSizeInBits();
-
-  return DestSize < SrcSize && DestSize % 32 == 0 ;
+  return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
 }
 
 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
   // Truncate is just accessing a subregister.
-
-  unsigned SrcSize = Source->getScalarSizeInBits();
-  unsigned DestSize = Dest->getScalarSizeInBits();
-
-  if (DestSize== 16 && Subtarget->has16BitInsts())
-    return SrcSize >= 32;
-
-  return DestSize < SrcSize && DestSize % 32 == 0;
+  return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
+         (Dest->getPrimitiveSizeInBits() % 32 == 0);
 }
 
 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
   unsigned SrcSize = Src->getScalarSizeInBits();
   unsigned DestSize = Dest->getScalarSizeInBits();
 
-  if (SrcSize == 16 && Subtarget->has16BitInsts())
-    return DestSize >= 32;
-
   return SrcSize == 32 && DestSize == 64;
 }
 
@@ -620,10 +607,6 @@ bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
   // practical purposes, the extra mov 0 to load a 64-bit is free.  As used,
   // this will enable reducing 64-bit operations the 32-bit, which is always
   // good.
-
-  if (Src == MVT::i16)
-    return Dest == MVT::i32 ||Dest == MVT::i64 ;
-
   return Src == MVT::i32 && Dest == MVT::i64;
 }
 
@@ -2463,10 +2446,6 @@ SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
   if (VT.isVector() || Size > 64)
     return SDValue();
 
-  // There are i16 integer mul/mad.
-  if (Subtarget->has16BitInsts() && VT.getScalarType().bitsLE(MVT::i16))
-    return SDValue();
-
   SelectionDAG &DAG = DCI.DAG;
   SDLoc DL(N);