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| author | Tom Stellard <thomas.stellard@amd.com> | 2016-10-14 19:14:29 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2016-10-14 19:14:29 +0000 |
| commit | 09c2bd6bd42acb172e847d5088014512e97b37f8 (patch) | |
| tree | 4b319e41158bfc149c71e9767fd96c771e07eddb /llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | |
| parent | ab610079142f420b09a10c3dfded03817bc1250d (diff) | |
| download | bcm5719-llvm-09c2bd6bd42acb172e847d5088014512e97b37f8.tar.gz bcm5719-llvm-09c2bd6bd42acb172e847d5088014512e97b37f8.zip | |
AMDGPU/SI: Use new SimplifyDemandedBits helper for multi-use operations
Summary:
We are using this helper for our 24-bit arithmetic combines, so we are now able to eliminate multi-use operations that mask the high-bits of 24-bit inputs (e.g. and x, 0xffffff)
Reviewers: arsenm, nhaehnle
Subscribers: tony-tye, arsenm, kzhuravl, wdng, nhaehnle, llvm-commits, yaxunl
Differential Revision: https://reviews.llvm.org/D24672
llvm-svn: 284267
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 23 |
1 files changed, 10 insertions, 13 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 6f75c9cd924..03833609a77 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -2022,19 +2022,18 @@ static bool isI24(SDValue Op, SelectionDAG &DAG) { (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24; } -static bool simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) { +static bool simplifyI24(SDNode *Node24, unsigned OpIdx, + TargetLowering::DAGCombinerInfo &DCI) { SelectionDAG &DAG = DCI.DAG; - const TargetLowering &TLI = DAG.getTargetLoweringInfo(); + SDValue Op = Node24->getOperand(OpIdx); EVT VT = Op.getValueType(); APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24); APInt KnownZero, KnownOne; TargetLowering::TargetLoweringOpt TLO(DAG, true, true); - if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) { - DCI.CommitTargetLoweringOpt(TLO); + if (TLO.SimplifyDemandedBits(Node24, OpIdx, Demanded, DCI)) return true; - } return false; } @@ -2424,13 +2423,13 @@ SDValue AMDGPUTargetLowering::performMulLoHi24Combine( SDNode *N, DAGCombinerInfo &DCI) const { SelectionDAG &DAG = DCI.DAG; - SDValue N0 = N->getOperand(0); - SDValue N1 = N->getOperand(1); - // Simplify demanded bits before splitting into multiple users. - if (simplifyI24(N0, DCI) || simplifyI24(N1, DCI)) + if (simplifyI24(N, 0, DCI) || simplifyI24(N, 1, DCI)) return SDValue(); + SDValue N0 = N->getOperand(0); + SDValue N1 = N->getOperand(1); + bool Signed = (N->getOpcode() == AMDGPUISD::MUL_LOHI_I24); unsigned MulLoOpc = Signed ? AMDGPUISD::MUL_I24 : AMDGPUISD::MUL_U24; @@ -2632,10 +2631,8 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N, case AMDGPUISD::MUL_U24: case AMDGPUISD::MULHI_I24: case AMDGPUISD::MULHI_U24: { - SDValue N0 = N->getOperand(0); - SDValue N1 = N->getOperand(1); - simplifyI24(N0, DCI); - simplifyI24(N1, DCI); + simplifyI24(N, 0, DCI); + simplifyI24(N, 1, DCI); return SDValue(); } case AMDGPUISD::MUL_LOHI_I24: |
