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author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-05-19 12:46:02 +0000 |
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committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-05-19 12:46:02 +0000 |
commit | ede0e4073e927fe690712a71f3c05586b476f0df (patch) | |
tree | b4dfa3bd508e2ae1f704ededbcf84f9ebd56fb0d /llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | |
parent | 0a0a4d77858a804f49c089b8fd06a31aca7abced (diff) | |
download | bcm5719-llvm-ede0e4073e927fe690712a71f3c05586b476f0df.tar.gz bcm5719-llvm-ede0e4073e927fe690712a71f3c05586b476f0df.zip |
Fix MSVC unused variable warning. NFCI.
AMDGPURegisterInfo::getSubRegFromChannel is a static method - we don't need to get the AMDGPURegisterInfo instance.
llvm-svn: 332807
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp')
-rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index 16fb438de01..e0114b8c825 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -393,7 +393,6 @@ void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) { EVT VT = N->getValueType(0); unsigned NumVectorElts = VT.getVectorNumElements(); EVT EltVT = VT.getVectorElementType(); - const AMDGPURegisterInfo *TRI = Subtarget->getRegisterInfo(); SDLoc DL(N); SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); @@ -419,10 +418,9 @@ void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) { IsRegSeq = false; break; } + unsigned Sub = AMDGPURegisterInfo::getSubRegFromChannel(i); RegSeqArgs[1 + (2 * i)] = N->getOperand(i); - RegSeqArgs[1 + (2 * i) + 1] = - CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL, - MVT::i32); + RegSeqArgs[1 + (2 * i) + 1] = CurDAG->getTargetConstant(Sub, DL, MVT::i32); } if (NOps != NumVectorElts) { // Fill in the missing undef elements if this was a scalar_to_vector. @@ -430,9 +428,10 @@ void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) { MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, EltVT); for (unsigned i = NOps; i < NumVectorElts; ++i) { + unsigned Sub = AMDGPURegisterInfo::getSubRegFromChannel(i); RegSeqArgs[1 + (2 * i)] = SDValue(ImpDef, 0); RegSeqArgs[1 + (2 * i) + 1] = - CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL, MVT::i32); + CurDAG->getTargetConstant(Sub, DL, MVT::i32); } } |