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authorTom Stellard <tstellar@redhat.com>2017-08-08 05:52:00 +0000
committerTom Stellard <tstellar@redhat.com>2017-08-08 05:52:00 +0000
commit03aa3aee114ff345c51527dd04602752958e71db (patch)
tree2bfd24ea890ccd45953fb06ab19d33d3c8ec5333 /llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
parent20287697f8c80bb17ae1b0b29678c80272eaa52a (diff)
downloadbcm5719-llvm-03aa3aee114ff345c51527dd04602752958e71db.tar.gz
bcm5719-llvm-03aa3aee114ff345c51527dd04602752958e71db.zip
AMDGPU: Fix warnings introduced by r310336
llvm-svn: 310337
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp')
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp6
1 files changed, 2 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 6ecbe2743af..dfa26c871bc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -383,7 +383,6 @@ static bool getConstantValue(SDValue N, uint32_t &Out) {
}
void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) {
- unsigned Opc = N->getOpcode();
EVT VT = N->getValueType(0);
unsigned NumVectorElts = VT.getVectorNumElements();
EVT EltVT = VT.getVectorElementType();
@@ -420,7 +419,7 @@ void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) {
}
if (NOps != NumVectorElts) {
// Fill in the missing undef elements if this was a scalar_to_vector.
- assert(Opc == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
+ assert(N->getOpcode() == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
DL, EltVT);
for (unsigned i = NOps; i < NumVectorElts; ++i) {
@@ -481,7 +480,6 @@ void AMDGPUDAGToDAGISel::Select(SDNode *N) {
case ISD::BUILD_VECTOR: {
EVT VT = N->getValueType(0);
unsigned NumVectorElts = VT.getVectorNumElements();
- EVT EltVT = VT.getVectorElementType();
if (VT == MVT::v2i16 || VT == MVT::v2f16) {
if (Opc == ISD::BUILD_VECTOR) {
@@ -498,7 +496,7 @@ void AMDGPUDAGToDAGISel::Select(SDNode *N) {
break;
}
- assert(EltVT.bitsEq(MVT::i32));
+ assert(VT.getVectorElementType().bitsEq(MVT::i32));
unsigned RegClassID = selectSGPRVectorRegClassID(NumVectorElts);
SelectBuildVector(N, RegClassID);
return;
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