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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-06-24 07:07:55 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-06-24 07:07:55 +0000 |
commit | 86de486d3129f8d3bc05e3241c06f374252ac776 (patch) | |
tree | d0c078cbffa4f19a3eaeaaa5c0f7a342e097cba1 /llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp | |
parent | 2efbb3f394bd95d7c07fdcdbc2ffd2647778d9b7 (diff) | |
download | bcm5719-llvm-86de486d3129f8d3bc05e3241c06f374252ac776.tar.gz bcm5719-llvm-86de486d3129f8d3bc05e3241c06f374252ac776.zip |
AMDGPU: Add stub custom CodeGenPrepare pass
This will do various things including ones
CodeGenPrepare does, but with knowledge of uniform
values.
llvm-svn: 273657
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp')
-rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp new file mode 100644 index 00000000000..3b415774df4 --- /dev/null +++ b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp @@ -0,0 +1,82 @@ +//===-- AMDGPUCodeGenPrepare.cpp ------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +/// \file +/// This pass does misc. AMDGPU optimizations on IR before instruction +/// selection. +// +//===----------------------------------------------------------------------===// + +#include "AMDGPU.h" +#include "AMDGPUSubtarget.h" + +#include "llvm/Analysis/DivergenceAnalysis.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/IR/InstVisitor.h" +#include "llvm/IR/IRBuilder.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" + +#define DEBUG_TYPE "amdgpu-codegenprepare" + +using namespace llvm; + +namespace { + +class AMDGPUCodeGenPrepare : public FunctionPass, + public InstVisitor<AMDGPUCodeGenPrepare> { + DivergenceAnalysis *DA; + const TargetMachine *TM; + +public: + static char ID; + AMDGPUCodeGenPrepare(const TargetMachine *TM = nullptr) : + FunctionPass(ID), + TM(TM) { } + + bool doInitialization(Module &M) override; + bool runOnFunction(Function &F) override; + + const char *getPassName() const override { + return "AMDGPU IR optimizations"; + } + + void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.addRequired<DivergenceAnalysis>(); + AU.setPreservesAll(); + } +}; + +} // End anonymous namespace + +bool AMDGPUCodeGenPrepare::doInitialization(Module &M) { + return false; +} + +bool AMDGPUCodeGenPrepare::runOnFunction(Function &F) { + if (!TM || skipFunction(F)) + return false; + + DA = &getAnalysis<DivergenceAnalysis>(); + visit(F); + + return true; +} + +INITIALIZE_TM_PASS_BEGIN(AMDGPUCodeGenPrepare, DEBUG_TYPE, + "AMDGPU IR optimizations", false, false) +INITIALIZE_PASS_DEPENDENCY(DivergenceAnalysis) +INITIALIZE_TM_PASS_END(AMDGPUCodeGenPrepare, DEBUG_TYPE, + "AMDGPU IR optimizations", false, false) + +char AMDGPUCodeGenPrepare::ID = 0; + +FunctionPass *llvm::createAMDGPUCodeGenPreparePass(const TargetMachine *TM) { + return new AMDGPUCodeGenPrepare(TM); +} |