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| author | Sander de Smalen <sander.desmalen@arm.com> | 2018-06-01 12:54:46 +0000 |
|---|---|---|
| committer | Sander de Smalen <sander.desmalen@arm.com> | 2018-06-01 12:54:46 +0000 |
| commit | f95ea047e566b1e27749f75a423c5b07c5329ec6 (patch) | |
| tree | e416e7a9e87975b7edb4d41911d3c0ae89c030c1 /llvm/lib/Target/AArch64 | |
| parent | a041d8483cbeab5580ebddeefd75b4a58359c7cb (diff) | |
| download | bcm5719-llvm-f95ea047e566b1e27749f75a423c5b07c5329ec6.tar.gz bcm5719-llvm-f95ea047e566b1e27749f75a423c5b07c5329ec6.zip | |
[AArch64][SVE] Asm: Support for FDUP_ZI (copy fp immediate) instruction.
Unpredicated copy of floating-point immediate value into SVE vector,
along with MOV-aliases.
Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D47482
llvm-svn: 333744
Diffstat (limited to 'llvm/lib/Target/AArch64')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/SVEInstrFormats.td | 38 |
2 files changed, 39 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 3207be74968..009afac6332 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -37,6 +37,7 @@ let Predicates = [HasSVE] in { // Splat immediate (unpredicated) defm DUP_ZI : sve_int_dup_imm<"dup">; + defm FDUP_ZI : sve_int_dup_fpimm<"fdup">; defm DUPM_ZI : sve_int_dup_mask_imm<"dupm">; // continuous load with reg+immediate diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 8794522c2c6..8b9eda16720 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -527,6 +527,44 @@ multiclass sve_int_dup_imm<string asm> { (!cast<Instruction>(NAME # _S) ZPR32:$Zd, cpy_imm8_opt_lsl_i32:$imm), 1>; def : InstAlias<"mov $Zd, $imm", (!cast<Instruction>(NAME # _D) ZPR64:$Zd, cpy_imm8_opt_lsl_i64:$imm), 1>; + + def : InstAlias<"fmov $Zd, #0.0", + (!cast<Instruction>(NAME # _H) ZPR16:$Zd, 0, 0), 1>; + def : InstAlias<"fmov $Zd, #0.0", + (!cast<Instruction>(NAME # _S) ZPR32:$Zd, 0, 0), 1>; + def : InstAlias<"fmov $Zd, #0.0", + (!cast<Instruction>(NAME # _D) ZPR64:$Zd, 0, 0), 1>; +} + +class sve_int_dup_fpimm<bits<2> sz8_64, Operand fpimmtype, + string asm, ZPRRegOp zprty> +: I<(outs zprty:$Zd), (ins fpimmtype:$imm8), + asm, "\t$Zd, $imm8", + "", + []>, Sched<[]> { + bits<5> Zd; + bits<8> imm8; + let Inst{31-24} = 0b00100101; + let Inst{23-22} = sz8_64; + let Inst{21-14} = 0b11100111; + let Inst{13} = 0b0; + let Inst{12-5} = imm8; + let Inst{4-0} = Zd; + + let isReMaterializable = 1; +} + +multiclass sve_int_dup_fpimm<string asm> { + def _H : sve_int_dup_fpimm<0b01, fpimm16, asm, ZPR16>; + def _S : sve_int_dup_fpimm<0b10, fpimm32, asm, ZPR32>; + def _D : sve_int_dup_fpimm<0b11, fpimm64, asm, ZPR64>; + + def : InstAlias<"fmov $Zd, $imm8", + (!cast<Instruction>(NAME # _H) ZPR16:$Zd, fpimm16:$imm8), 1>; + def : InstAlias<"fmov $Zd, $imm8", + (!cast<Instruction>(NAME # _S) ZPR32:$Zd, fpimm32:$imm8), 1>; + def : InstAlias<"fmov $Zd, $imm8", + (!cast<Instruction>(NAME # _D) ZPR64:$Zd, fpimm64:$imm8), 1>; } class sve_int_arith_imm0<bits<2> sz8_64, bits<3> opc, string asm, |
