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| author | Quentin Colombet <qcolombet@apple.com> | 2015-05-01 20:57:11 +0000 |
|---|---|---|
| committer | Quentin Colombet <qcolombet@apple.com> | 2015-05-01 20:57:11 +0000 |
| commit | 9df2fa261b66933cf0f3f8882e5ea0eee9fbc075 (patch) | |
| tree | 36abccc3f9cf97a092c60411d16ef74feddd00a1 /llvm/lib/Target/AArch64 | |
| parent | 292e92d99de0d58c91a7278aa788339c15f86275 (diff) | |
| download | bcm5719-llvm-9df2fa261b66933cf0f3f8882e5ea0eee9fbc075.tar.gz bcm5719-llvm-9df2fa261b66933cf0f3f8882e5ea0eee9fbc075.zip | |
[AArch64][FastISel] Fix the setting of kill flags for MUL -> UMULH sequences.
rdar://problem/20748715
llvm-svn: 236346
Diffstat (limited to 'llvm/lib/Target/AArch64')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64FastISel.cpp | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp index 837a31f303f..c70b17c8a32 100644 --- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp +++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp @@ -3598,7 +3598,10 @@ bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) { AArch64_AM::ASR, 31, /*WantResult=*/false); } else { assert(VT == MVT::i64 && "Unexpected value type."); - MulReg = emitMul_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill); + // LHSReg and RHSReg cannot be killed by this Mul, since they are + // reused in the next instruction. + MulReg = emitMul_rr(VT, LHSReg, /*IsKill=*/false, RHSReg, + /*IsKill=*/false); unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, LHSIsKill, RHSReg, RHSIsKill); emitSubs_rs(VT, SMULHReg, /*IsKill=*/true, MulReg, /*IsKill=*/false, @@ -3627,7 +3630,10 @@ bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) { AArch64::sub_32); } else { assert(VT == MVT::i64 && "Unexpected value type."); - MulReg = emitMul_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill); + // LHSReg and RHSReg cannot be killed by this Mul, since they are + // reused in the next instruction. + MulReg = emitMul_rr(VT, LHSReg, /*IsKill=*/false, RHSReg, + /*IsKill=*/false); unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, LHSIsKill, RHSReg, RHSIsKill); emitSubs_rr(VT, AArch64::XZR, /*IsKill=*/true, UMULHReg, |

