GlobalISel: implement low-level type with just size & vector lanes.

This should be all the low-level instruction selection needs to determine how
to implement an operation, with the remaining context taken from the opcode
(e.g. G_ADD vs G_FADD) or other flags not based on type (e.g. fast-math).

llvm-svn: 276158

2 files changed, 27 insertions, 0 deletions

diff --git a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
index 0a1831bd9a8..c415c7bf16a 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
@@ -155,6 +155,7 @@ AArch64RegisterBankInfo::getInstrAlternativeMappings(
 void AArch64RegisterBankInfo::applyMappingImpl(
     const OperandsMapper &OpdMapper) const {
   switch (OpdMapper.getMI().getOpcode()) {
+  case TargetOpcode::G_ADD:
   case TargetOpcode::G_OR: {
     // Those ID must match getInstrAlternativeMappings.
     assert((OpdMapper.getInstrMapping().getID() == 1 ||
@@ -166,3 +167,27 @@ void AArch64RegisterBankInfo::applyMappingImpl(
     llvm_unreachable("Don't know how to handle that operation");
   }
 }
+
+RegisterBankInfo::InstructionMapping
+AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
+  RegisterBankInfo::InstructionMapping Mapping = getInstrMappingImpl(MI);
+  if (Mapping.isValid())
+    return Mapping;
+
+  // As a top-level guess, vectors go in FPRs, scalars in GPRs. Obviously this
+  // won't work for normal floating-point types (or NZCV). When such
+  // instructions exist we'll need to look at the MI's opcode.
+  LLT Ty = MI.getType();
+  unsigned BankID;
+  if (Ty.isVector())
+    BankID = AArch64::FPRRegBankID;
+  else
+    BankID = AArch64::GPRRegBankID;
+
+  Mapping = InstructionMapping{1, 1, MI.getNumOperands()};
+  int Size = Ty.isSized() ? Ty.getSizeInBits() : 0;
+  for (unsigned Idx = 0; Idx < MI.getNumOperands(); ++Idx)
+    Mapping.setOperandMapping(Idx, Size, getRegBank(BankID));
+
+  return Mapping;
+}
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.h b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.h
index 907bcfdea16..a051a969dac 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.h
@@ -64,6 +64,8 @@ public:
   /// Alternative in the sense different from getInstrMapping.
   InstructionMappings
   getInstrAlternativeMappings(const MachineInstr &MI) const override;
+
+  InstructionMapping getInstrMapping(const MachineInstr &MI) const override;
 };
 } // End llvm namespace.
 #endif