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authorEvandro Menezes <e.menezes@samsung.com>2019-11-04 16:12:09 -0600
committerEvandro Menezes <e.menezes@samsung.com>2019-11-04 16:21:28 -0600
commit4cbe10efc2011641f72357685feff35ca87ed0d5 (patch)
tree4221c1f4317098576fa00b693311a63197ae5095 /llvm/lib/Target/AArch64
parent1cce82eae84a65fc03402f90a67b5b804d02dd6c (diff)
downloadbcm5719-llvm-4cbe10efc2011641f72357685feff35ca87ed0d5.tar.gz
bcm5719-llvm-4cbe10efc2011641f72357685feff35ca87ed0d5.zip
[AArch64] Update for Exynos
Fix the costs of integer division.
Diffstat (limited to 'llvm/lib/Target/AArch64')
-rw-r--r--llvm/lib/Target/AArch64/AArch64SchedExynosM4.td6
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
index 447cdee1679..60a6a2bbd5f 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
@@ -175,8 +175,10 @@ def M4WriteC3 : SchedWriteRes<[M4UnitC]> { let Latency = 3; }
def M4WriteCA : SchedWriteRes<[M4UnitC]> { let Latency = 4;
let ResourceCycles = [2]; }
-def M4WriteD12 : SchedWriteRes<[M4UnitD]> { let Latency = 12; }
-def M4WriteD21 : SchedWriteRes<[M4UnitD]> { let Latency = 21; }
+def M4WriteD12 : SchedWriteRes<[M4UnitD]> { let Latency = 12;
+ let ResourceCycles = [12]; }
+def M4WriteD21 : SchedWriteRes<[M4UnitD]> { let Latency = 21;
+ let ResourceCycles = [21]; }
def M4WriteE2 : SchedWriteRes<[M4UnitE]> { let Latency = 2; }
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