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| author | Jingyue Wu <jingyue@google.com> | 2014-10-04 03:50:10 +0000 |
|---|---|---|
| committer | Jingyue Wu <jingyue@google.com> | 2014-10-04 03:50:10 +0000 |
| commit | 4938e271c6a3a646a805bf10e7ae5fd859cedc62 (patch) | |
| tree | 54566aa504bd16bc5206f8a3a54a58dca488ce9e /llvm/lib/Target/AArch64 | |
| parent | 200e87c0c59d88b1dddd12295a87f60fa2edfa41 (diff) | |
| download | bcm5719-llvm-4938e271c6a3a646a805bf10e7ae5fd859cedc62.tar.gz bcm5719-llvm-4938e271c6a3a646a805bf10e7ae5fd859cedc62.zip | |
Add fake use to suppress defined-but-unused warnings
llvm-svn: 219045
Diffstat (limited to 'llvm/lib/Target/AArch64')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64FastISel.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp index 873b2ec328e..bf3d18343d1 100644 --- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp +++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp @@ -3304,6 +3304,7 @@ bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) { ResultReg2 = fastEmitInst_rri(AArch64::CSINCWr, &AArch64::GPR32RegClass, AArch64::WZR, /*IsKill=*/true, AArch64::WZR, /*IsKill=*/true, getInvertedCondCode(CC)); + (void)ResultReg2; assert((ResultReg1 + 1) == ResultReg2 && "Nonconsecutive result registers."); updateValueMap(II, ResultReg1, 2); |
